In communications systems, a transmitter sends data streams to a receiver in symbols, such as bits of data. In frame-based data transmission, data is transmitted in frames of a fixed length, and the transmitter and the receiver agree ahead of time on a selected frame synchronization scheme, including choice of a synchronization marker. At the transmitter, the synchronization marker is embedded in a frame as frame-based point of reference such that the receiver can identify boundaries of the frames. The synchronization marker is commonly known as frame alignment signal (FAS), frame alignment word (FAW), framing pattern, or frame alignment pattern (FAP).
Typically, an embedded FAW includes a fixed number of bits in a pattern known at the receiver side and is located in the overhead section of the frame, usually the first time slot in a frame before the payload data. For an alignment mechanism to be maintained, a FAW may be transmitted in every frame, or in another predetermined frequency, such as in every 3rd frame, every 5th frame, and etc.
Correspondingly, the receiver utilizes a synchronization mechanism to detect the FAW in the data stream and thereby synchronize the data stream. More specifically, one or more framer circuits (or referred to as “framers” herein) in the receiver perform a frame alignment process to detect the boundary of a respective transmission frame and align the internal or embedded data to the data stream. Once frame synchronization (or frame alignment) is obtained, the data stream is subject to further data processing at the receiver.
Low power consumption in integrated circuits has increasingly become important in high speed communications systems, especially in power-sensitive applications, such as data center installations (e.g., server cards, Top-of-Rack (ToR) switches, board interconnection), optical modules which typically have a tight power budget, high density Ethernet cards in which cooling the system is critical and costly, and others.
In conventional high-speed PHY chips, after frame alignment is obtained, a framer continues to actively search for the fixed FAW in expected frame locations in a periodic fashion, and declares “out-of-frame” when the there is no match for a number of times. Thus, framers are kept active for the whole time the system is operational. The continuous operations of framers contribute to undesirable significant power consumption in a receiver.
Moreover, current framers use multiple identical copies of the same circuit (typically comparators) to compare a fixed FAW with the incoming data in parallel, each comparator looking at a different portion (a “window”) of the parallel data bus. The number of comparators equals to the number of all the windows to be checked with respect to the parallel data bus. In addition, current receivers use one framer for each physical lane. Due to the high number of comparator gates used in such configurations, the power consumption associated with the toggling of these gates is undesirably high.